FPGA verification and emulation of the analog TV-IF demodulator SoC

Abstract

In this paper, we present one approach to the realtime verification of the DSP-based analog TV-IF demodulator on Field Programmable Gate Array (FPGA). The demodulator performs entire multistandard TV-IF processing of analog input TV signal. The entire system is controlled by programmable 8 bit CPU core. The demodulator and CPU reference models are written in C++ language, and represent only behavioral models. In order to describe concurrency and clocking (cycle dependent simulation) we used SystemC as inter-level between behavioral and RTL model. Verilog hardware description language is used to describe RTL model for FPGA implementation. © 2006 by MIPRO. All rights reserved.