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https://open.uns.ac.rs/handle/123456789/8399
Title: | FPGA verification and emulation of the analog TV-IF demodulator SoC | Authors: | Cvejanovic D. Katona M. Maluckov N. Nikolić, Milica Simeonov A. Teslić, Nikola |
Issue Date: | 1-Jan-2006 | Journal: | MIPRO 2006 - 29th International Convention Proceedings: Computers in Technical Systems and Intelligent Systems | Abstract: | In this paper, we present one approach to the realtime verification of the DSP-based analog TV-IF demodulator on Field Programmable Gate Array (FPGA). The demodulator performs entire multistandard TV-IF processing of analog input TV signal. The entire system is controlled by programmable 8 bit CPU core. The demodulator and CPU reference models are written in C++ language, and represent only behavioral models. In order to describe concurrency and clocking (cycle dependent simulation) we used SystemC as inter-level between behavioral and RTL model. Verilog hardware description language is used to describe RTL model for FPGA implementation. © 2006 by MIPRO. All rights reserved. | URI: | https://open.uns.ac.rs/handle/123456789/8399 |
Appears in Collections: | FTN Publikacije/Publications |
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