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https://open.uns.ac.rs/handle/123456789/8698
Nаziv: | An approach to instruction set compiled simulator development based on a target processor C compiler back-end design | Аutоri: | Djukic M. Cetic N. Obradović, Ratko Popović, Miroslav |
Dаtum izdаvаnjа: | 1-сеп-2013 | Čаsоpis: | Innovations in Systems and Software Engineering | Sažetak: | Many instruction set simulation approaches place the retargetability and/or cycle-accuracy as the key features for easier architectural exploration and performance estimation early in the hardware development phase. This paper describes an approach in which importance of speed and controllability is placed above the cycle-accuracy and retargetability, thus providing a better platform for software development. The main idea behind this work is to associate the compiled simulator effort with the development of the C language compiler for the target embedded processor, using the knowledge related to compilers and reusing some common software elements. Through the prototype design of a compiled simulator for the Cirrus Logic Coyote DSP architecture, many implementation aspects are presented showing that this approach has great potential. © 2013 Springer-Verlag London. | URI: | https://open.uns.ac.rs/handle/123456789/8698 | ISSN: | 16145046 | DOI: | 10.1007/s11334-013-0220-0 |
Nаlаzi sе u kоlеkciјаmа: | FTN Publikacije/Publications |
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