Please use this identifier to cite or link to this item: https://open.uns.ac.rs/handle/123456789/5318
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dc.contributor.authorPajkanovic A.en
dc.date.accessioned2019-09-30T08:47:12Z-
dc.date.available2019-09-30T08:47:12Z-
dc.date.issued2015-10-28en
dc.identifier.isbn9781467370165en
dc.identifier.urihttps://open.uns.ac.rs/handle/123456789/5318-
dc.description.abstract© 2015 IEEE. In this paper an operational amplifier of general purpose is presented. The unified current-control model is used to synthesize a standard, two-stage topology based circuit. The design procedure is discussed thoroughly and every step is explained in details. The results obtained include open loop gain of 74 dB, the gain-bandwidth product of 100 MHz and the phase margin higher than 46°. Supply voltage and temperature coefficients are analyzed and discussed within the paper. Process variations are investigated through corner analysis. The results presented are obtained through schematic level simulations using the Spectre Simulator from Cadence Design System and a standard 130 nm CMOS technology process.en
dc.relation.ispartofProceedings - 7th International Conference on Computational Intelligence, Communication Systems and Networks, CICSyN 2015en
dc.titleA 130 Nm Operational Amplifier: Design and Schematic Level Simulationen
dc.typeConference Paperen
dc.identifier.doi10.1109/CICSyN.2015.50en
dc.identifier.scopus2-s2.0-84962053081en
dc.identifier.urlhttps://api.elsevier.com/content/abstract/scopus_id/84962053081en
dc.relation.lastpage254en
dc.relation.firstpage249en
item.grantfulltextnone-
item.fulltextNo Fulltext-
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