IP core for AES256 and TDES algorithms with AXI interface

Abstract

© 2016 IEEE. Algorithms for data encryption are one of the most important parts of modern communication systems. In this paper the results of hardware implementation of AES256 and TDES algorithms are presented. AES256 and TDES are implemented as an IP core with AXI interface because of constant growth of data transfer requirements in modern embedded systems, in order to improve their capability. Beside details about the implementation of these algorithms, acceleration gain, compared to the software implementation, is also presented. It is shown that the performance of FPGA implementation of proposed IP core is approximately 13 to 416 times faster compared to the software implementation using standard ARM based architecture, and comparable to that of modern Intel processors with AES specific Instruction Set.