Please use this identifier to cite or link to this item: https://open.uns.ac.rs/handle/123456789/13523
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dc.contributor.authorMajstorović D.en
dc.contributor.authorPele Z.en
dc.contributor.authorKovačević, Aleksandaren
dc.contributor.authorČelanović N.en
dc.date.accessioned2020-03-03T14:52:41Z-
dc.date.available2020-03-03T14:52:41Z-
dc.date.issued2009-01-01en
dc.identifier.isbn9780769537597en
dc.identifier.urihttps://open.uns.ac.rs/handle/123456789/13523-
dc.description.abstractThis paper defines a highly optimized computer architecture and FPGA technology as the most feasible approach to satisfy the challenging requirements defined by the need to emulate power electronics hardware with sub-microsecond latency and sampling time. The proposed commercial of the shelf computational platforms and the accompanying software tools based on the industry standard software platform have the potential to bring qualitative improvements in the way how power electronics software is designed, how it is tested and how its performance is verified. © 2009 IEEE.en
dc.relation.ispartofECBS-EERC 2009 - 1st Eastern European Regional Conference on the Engineering of Computer-Based Systems: Setting New ECBS Frontiers.en
dc.titleComputer based emulation of power electronics hardwareen
dc.typeConference Paperen
dc.identifier.doi10.1109/ECBS-EERC.2009.20en
dc.identifier.scopus2-s2.0-74349100059en
dc.identifier.urlhttps://api.elsevier.com/content/abstract/scopus_id/74349100059en
dc.relation.lastpage64en
dc.relation.firstpage56en
item.fulltextNo Fulltext-
item.grantfulltextnone-
crisitem.author.deptDepartman za računarstvo i automatiku-
crisitem.author.parentorgFakultet tehničkih nauka-
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