Numerical analysis of DGMOSFET 1/f noise under different bias conditions

Abstract

In this paper ID VDS characteristics and numerical analysis of 1/f noise for DGMOSFET and its transistors are presented. A model of DGMOSFET noise analysis based on small signal noise equivalent circuits is proposed. Using this model we have calculated the weighting factors that describe participation of source and drain transistor noises in total noise. It is found that DGMOSFET 1/f noise is lower than noise of the first (source) and second (drain) transistors if the first transistor is in linear or partially non-linear regions. Moreover, resultant DGMOSFET noise is lower than source transistor noise under all bias conditions. If source and drain transistors are in non-linear and/or saturation regimes, the source transistor dominantly influences DGMOSFET noise. ©2005 IEEE.