Modeling and verifying transaction scheduling for software transactional memory using CSP

Abstract

© 2019 IEEE. Transaction Memory (TM) is designed for simplifying parallel programming, while some key problems exist in it, such as starvation and reduced performance with high contention among transactions. In order to improve the performance of TM, researchers have designed several transaction scheduling algorithms and given their experimental results. However, the evaluations on the algorithms given by these researches are rather partial and lack of generality. Since these experimental results ignore the verification of properties which are necessary for transaction scheduling and could be greatly affected by the execution environment, thus it is still challenging for us to judge the quality of the algorithms for TM. In this paper, we provide a formal approach to evaluate transaction scheduling algorithms in a more comprehensive and strict way. We choose three recently proposed algorithms as motivating examples and formalize them using the process algebra CSP. We also use a model checker PAT to verify the properties (e.g., deadlock freeness and starvation freeness) of the models. Besides, it is also easier to compare the performance of the algorithms, from the perspective of makespan, speedup, aborts time and throughput, based on the statistics given by PAT. Consequently, a formal approach can be achieved to evaluate transaction scheduling algorithms, which is also a good guide for the further design of the algorithms for TM.