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https://open.uns.ac.rs/handle/123456789/11336
Title: | FIR filter implementation for high- performance application in a high-end FPGA | Authors: | Pijetlović, Stefan Subotić M. Marinković, Vladimir Pjevalica, Nebojša |
Issue Date: | 1-Jan-2019 | Journal: | Telfor Journal | Abstract: | © 2019, Telecommunications Society and Academic Mind. In this paper a high-performance application which uses multiple 48k tap FIR filters is presented. Due to its size, complexity and restrictions such as real-time, small latency and large memory bandwidth, the filter was implemented in UltraScale+, a high-end FPGA from Xilinx. The system was verified using a gold reference model written in C (high-level algorithm verification) and an analytical model calculated manually. The system was also tested using a development board and SystemVerilog (for register-transfer level and timing verification). The obtained results show a perfect match between the reference models and the actual output. The main novelty of the paper is the implementation of such an immense real-time signal processing system based on FIR filters consisting of over a million taps all together in a single design spread out across a chip containing three dies. Details about the resources allocated within the FPGA are also given in a table in the results chapter. | URI: | https://open.uns.ac.rs/handle/123456789/11336 | ISSN: | 18213251 | DOI: | 10.5937/telfor1901041P |
Appears in Collections: | FTN Publikacije/Publications |
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