Please use this identifier to cite or link to this item: https://open.uns.ac.rs/handle/123456789/15470
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dc.contributor.authorVekić, Markoen
dc.contributor.authorGrabić, Stevanen
dc.contributor.authorMajstorović D.en
dc.contributor.authorČelanović I.en
dc.contributor.authorČelanović N.en
dc.contributor.authorKatić, Vladimiren
dc.date.accessioned2020-03-03T15:00:05Z-
dc.date.available2020-03-03T15:00:05Z-
dc.date.issued2012-07-03en
dc.identifier.issn8858993en
dc.identifier.urihttps://open.uns.ac.rs/handle/123456789/15470-
dc.description.abstractPrototyping and verification of complex power electronics (PE) systems and control algorithms is a laborious and time-consuming process. Even when a low-power hardware model is assembled, it enables only a limited insight into the large number of operating points; changes in system parameters regularly demand hardware modifications and always there is the risk of hardware damage. The ultralow-latency Hardware-In-the-Loop (HIL) platform proposed in this paper combines the flexibility, accuracy, and ease of use of state-of-the-art- simulation packages, with the response speed of small power-hardware models. In this way, PE systems-optimization, code-development, and laboratory-testing can be combined into one step, which dramatically accelerates the pace of product prototyping. Low-power hardware-models also suffer from nonscalability, because some parameters such as electrical machine inertia cannot be properly scaled. However, HIL enables control prototyping that covers all operational conditions. In order to demonstrate HIL-based rapid development, the verification of an active damping algorithm for a permanent magnet synchronous generator (PMSG) cascade is performed. Two goals are set in this paper: to verify the developed HIL platform by means of comparison with a low-power hardware setup and then to emulate the real, high-power system in order to test the active damping algorithm. © 2012 IEEE.en
dc.relation.ispartofIEEE Transactions on Power Electronicsen
dc.titleUltralow latency HIL platform for rapid development of complex power electronics systemsen
dc.typeJournal/Magazine Articleen
dc.identifier.doi10.1109/TPEL.2012.2190097en
dc.identifier.scopus2-s2.0-84862989900en
dc.identifier.urlhttps://api.elsevier.com/content/abstract/scopus_id/84862989900en
dc.relation.lastpage4444en
dc.relation.firstpage4436en
dc.relation.issue11en
dc.relation.volume27en
item.fulltextNo Fulltext-
item.grantfulltextnone-
crisitem.author.deptFakultet tehničkih nauka, Departman za energetiku, elektroniku i telekomunikacije-
crisitem.author.deptFakultet tehničkih nauka, Departman za energetiku, elektroniku i telekomunikacije-
crisitem.author.parentorgFakultet tehničkih nauka-
crisitem.author.parentorgFakultet tehničkih nauka-
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